Due to the growing complexity of integrated circuits on semiconductor substrates or chips and the asynchronous nature of power source and clock inputs, when a system on a chip is powered up, reliable power on reset circuits are becoming of critical importance in integrated circuit technology. A reliable power on reset pulse greatly simplifies and improves the reliability of circuit designs for, e.g., enabling redundancy, maintaining off chip drivers in a tri-state condition during power up and controlling clock logic so that the integrated circuit does not power up into an undesirable mode.
In most previously designed integrated circuits, power on reset circuits were not required because it was assumed that the circuit or system would control clock inputs during the power on state, there were fewer components on a circuit card and, therefore, even when clock inputs were uncontrolled, off chip driver circuit contention on data buses was not a significant problem and redundant circuits were simpler, merely using a NOR circuit of n fuses in series with n pull down field effect transistors.
As the level of integration on a chip increases, the need for reliable power on reset circuits increases since the sophisticated power on control logic available with larger systems such as main-frames and mid-frames is no longer available in low-ended systems, e.g., personal computer systems and workstations. Also, newer technologies have led to the capability of packing a far larger number of integrated circuits on cards, wherein off chip driver circuit contention on data buses can abort a power on sequence due to current overload, redundant circuits are becoming more sophisticated and often more numerous for optimal area and performance of circuits, and on chip clock logic is getting more sophisticated due to the need for handling new functions that are invoked during specific permutations of logic signals, such as for test mode entry. Accordingly, integrated circuit semiconductor chips employing advanced technology are more prone to powering up into a false state when not provided with a reliable power on reset circuit.
A number of power up detection or power on reset circuits have been proposed, such as in U.S. pat. No. 4,300,065, by J. J. Remedi et al, issued on Nov. 10, 1981, disclosing a power on reset circuit including a threshold detector which provides an output when the power supply voltage exceeds a transistor threshold voltage by approximately half a volt and a capacitor connected to the positive power supply terminal for widening the output pulse when the power supply rises at a slow rate. U.S. Pat. No. 4,591,745, by S. N. Shen, issued May 27, 1986, discloses a power-on reset pulse generator which includes an R-C network and a latch. Also, U.S. Pat. No. 4,902,907, by A. Haga et al, issued on Feb. 20, 1990, teaches a reset signal generating circuit which includes a first switch controlled by a divided voltage from a voltage dividing circuit turned on when the power source voltage rises to a value in the vicinity of a predetermined value with an arbitrary rising speed and a second switch turned on by the first switch and connected to a capacitor for charging and discharging the capacitor to provide a reset signal. Furthermore, U.S. Pat. No. 4,983,857, by R. C. Steele, issued on Jan. 8, 1991, discloses a power-up reset circuit which includes first and second serially connected field effect transistors disposed between a power supply voltage and an input of an inverter, a capacitor connected between the input of the inverter and the low supply voltage, with current flowing through the field effect transistors to charge the capacitor only when the supply voltage is greater than the sum of the absolute values of their threshold voltages and a depletion mode transistor shunting to ground any subthreshold leakage through the first and second transistors. Additionally, U.S. Pat. No. 5,030,845, by A. M. Love et al, issued Jul. 9, 1991, discloses a power-up pulse generator circuit in which channel width-to-length ratios of transistors are used to control a subthreshold current during the initial part of the power-up transient.
Prior art for power up detect circuits generally features components connected to an effective RC delay circuit. The delayed mode is then compared to, e.g., the power supply to determine that sufficient voltage has been applied to the integrated circuit chip for proper circuit operation. This type of power up detect circuit may operate satisfactorily in applications where power supply ramp rates are relatively fast, such as in circuit testers and personal computers, but it becomes less reliable in larger systems where ramp rates are several hundred milli-seconds. Effective power up detect circuits must be able to function reliably in systems having very fast to very slow power supply ramp rates.